1. Field of the Invention
The present invention generally relates to a substrate processing apparatus, a substrate processing method and a substrate holding member.
2. Description of the Related Art
Along with progressive miniaturization of circuit patterns of semiconductor devices, a variety of films making up semiconductor devices is demanded to be made thinner and more uniform. In order to respond to the demand, as described in Japanese Laid-Open Patent Application Publication No. 2010-56470, so-called MLD (Molecular Layer Deposition) and ALD (Atomic Layer Deposition) are known as film deposition methods. In the methods, a first reaction gas is adsorbed on a surface of a substrate by supplying the first reaction gas to the substrate, and then a second reaction gas is caused to react with the first reaction gas adsorbed on the surface of the substrate by supplying the second reaction gas to the substrate, thereby depositing a film made of a reaction product on the substrate. According to the film deposition methods, because the reaction gases can adsorb on the surface of the substrate in a quasi-self-saturated manner, high film deposition controllability, excellent uniformity, and superior filling characteristics can be achieved.
However, as aspect ratios of trenches in trench element isolation structures and spaces in line and space patterns increase along with the miniaturization of circuit patterns, filling the trenches and spaces is sometimes difficult even in the molecular layer deposition.
For example, when a space having a width of about 30 nm is tried to be filled with a silicon oxide film, because a reaction gas is unlikely to go into the bottom portion having a narrow space, film thicknesses near the top portion of a side wall forming the space is likely to become thick and to become thin on the bottom side. Because of this, a void may be generated in a silicon oxide film filled in the space. When such a silicon oxide film is etched in an etching process, for example, an opening in communication with the void may be formed in the top surface of the silicon oxide film. On this occasion, contamination is liable to occur because an etching gas (or an etching solution) goes into the void from the opening or a defect is liable to occur because a metal goes into the void during metallization performed later.
Such problems are not limited to MLD, and may occur even in CVD (Chemical Vapor Deposition). For example, when forming a conductive connection hole (i.e., so-called plug) by filling the connection hole with a conductive material, a void may be formed in the plug. Therefore, Japanese Laid-Open Patent Application Publication No. 2003-142484 proposes a method for forming a conductive connection hole (i.e., so-called plug) in which a void is prevented. In the method, a process of removing an overhanging portion of a conductive material formed over the connection hole in filling up the connection hole with the conductive material is repeated in order to prevent generation of the void.
However, in the method described in Japanese Laid-Open Patent Application Publication No. 2003-142484, because the film deposition of the conductive material and the etch back have to be performed by different apparatuses, it takes time to transfer the substrate between the apparatuses and to stabilize process conditions in each of the apparatuses, thereby deteriorating throughput. To solve the problem, Japanese Laid-Open Patent Application Publication No. 2015-19075 proposes a film deposition apparatus and a film deposition method in which a turntable-type ALD apparatus performs a V-letter etching process at high speed in situ.
According to the apparatus and method described in Japanese Laid-Open Patent Application Publication No. 2015-19075, a depressed portion formed in a substrate can be filled up with a film at high throughput while reducing the generation of a void.
However, when filling the depressed portion of a circuit pattern formed in a substrate with a film and then etching the film, if the shape of the depressed portion is fairly complex, because a surface area greatly increases compared to a flat portion, a great difference in the surface area is generated between the portion having the complex circuit pattern and the flat portion in which the circuit pattern is hardly formed. In such a case, when etching the film after depositing the film, a small amount of etching gas is consumed in the flat portion having the small surface area while a large amount of etching gas is consumed in the portion having the large surface area due to a loading phenomenon. However, because an amount of supply of the etching gas is almost uniform for the whole surface of the substrate, an etching rate decreases in the portion with the complex circuit pattern and the etching rate increases in the portion with the simple circuit pattern, which makes it difficult to maintain the favorable uniformity of the etching across the surface of the substrate. Moreover, such a phenomenon can occur in all substrate processes in which the loading phenomenon occurs.
Meanwhile, Japanese Laid-Open Patent Application Publication No. 2015-173154 proposes a film deposition process using a vertical thermal processing apparatus in which a gas distribution adjustment member is disposed above and below a wafer boat to adjust the gas distribution in the vertical direction, thereby being intended to improve the uniformity of the film deposition process in the vertical direction. However, because the technique differs from the film deposition process and the etching process using the turntable, the technique is difficult to apply to the turntable-type substrate processing apparatus.